Dynamic triggering and sampling engine (DTSE) for low-latency and cost effective control systems

ABSTRACT

A Dynamic Triggering and Sample Engine (DTSE) that detects a first trigger received on a trigger input terminal that triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit. The DTSE then determines a first sequence configuration stored in a sequence configuration table that is associated with the first trigger, causes a first analog-to-digital conversion to be performed using the first sequence configuration; causes a first analog-to-digital conversion result value to be stored in a sequence result table; and outputs an interrupt to a processor indicating that the first analog-to-digital conversion result value is available in the sequence result table. The interrupt is output from the DTSE before all remaining analog-to-digital conversions in the series are completed. In response to receiving the interrupt, the processor reads the analog-to-digital result value from the sequence result table via a bus.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of, and claims priority under 35U.S.C. § 120 from, nonprovisional U.S. patent application Ser. No.15/427,034 entitled “Dynamic Triggering and Sampling Engine (DTSE) forLow-Latency and Cost Effective Control Systems,” filed on Feb. 7, 2017,now U.S. Pat. No. 9,774,341. The entire subject matter of theaforementioned patent document is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to control systems, and morespecifically to a controller including a Dynamic Triggering and SamplingEngine (DTSE).

BACKGROUND INFORMATION

Control systems must meet complex design requirements when samplinganalog signals, such as, current, voltage or temperature. One example inwhich analog signals, such as, current, voltage and temperature arerequired to be sampled is in a Brushless Direct-Current (BLDC) electricmotor controller. Another example in which these analog signals arerequired to be sampled is in a Permanent-Magnet Synchronous Motor (PMSM)controller. These analog signals are also required to be sampled inmotor controllers and digitally controlled power supplies. Traditionalcontrollers require a designer to choose between high performance at ahigh cost, or reduced performance at an economical price. A highperformance solution that can be implemented at an economical price isneeded.

SUMMARY

In a first novel aspect, a Dynamic Triggering and Sample Engine (DTSE),includes a hardware trigger input, a bus terminal, a memory that storesa trigger mapping table, a sequence configuration table, a sequenceresult table, and a state machine. The state machine is configured to:detect a first trigger received on the hardware trigger input (the firsttrigger triggers a series of analog-to-digital conversions to becompleted by an analog-to-digital converter circuit); determine a firstsequence configuration stored in the sequence configuration table thatis associated with the first trigger; cause one of the firstanalog-to-digital conversions to be performed using the first sequenceconfiguration; cause a first analog-to-digital conversion result valueto be stored in the sequence result table; and output an interruptindicating that the first analog-to-digital conversion has beencompleted by the analog-to-digital circuit. In one example, theinterrupt is output before at least one of the remaininganalog-to-digital conversions in the series is completed. The statemachine may be implemented using combinatory logic or may be implementedusing a microcontroller.

In one example, the series of analog-to-digital conversions includescritical samples and non-critical samples, and at least one of thecritical samples is completed before at least one of the non-criticalsamples. The interrupt is output after at least one of the criticalsamples of the series of analog-to-digital conversions is completed.

In a second novel aspect, a method of dynamic triggering, includes:detecting a first trigger received on a hardware trigger input, wherethe first trigger triggers a series of analog-to-digital conversions tobe completed by an analog-to-digital converter circuit; determining afirst sequence configuration stored in a sequence configuration tablethat is associated with the first trigger; causing a firstanalog-to-digital conversion to be performed using the first sequenceconfiguration; causing a first analog-to-digital conversion result valueto be stored in a sequence result table; and outputting an interruptindicating that the first analog-to-digital conversion result value isavailable in the sequence result table. The interrupt is output beforeat least one of the analog-to-digital conversions in the series iscompleted.

In one example, the method of dynamic triggering further includes:determining a first portion of the series of analog-to-digitalconversions that are critical conversions; determining a second portionof the series of analog-to-digital conversions that are non-criticalconversions; and outputting the interrupt after at least one of thecritical conversions are completed and before the non-criticalconversions are completed.

The foregoing is a summary and thus contains, by necessity,simplifications, generalizations and omissions of detail; consequentlyit is appreciated that the summary is illustrative only. Still othermethods, and structures and details are set forth in the detaileddescription below. This summary does not purport to define theinvention. The invention is defined by the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, where like numerals indicate like components,illustrate embodiments of the invention.

FIG. 1 is a diagram of a traditional controller.

FIG. 2 is a diagram illustrating the operation of a controller withoutan auto-sequencer.

FIG. 3 is a diagram illustrating the operation of a controller with anauto-sequencer.

FIG. 4 is a diagram of a controller including a Dynamic Triggering andSample Engine (DTSE).

FIG. 5 is a more detailed diagram the DTSE of FIG. 4.

FIG. 6 is a diagram illustrating the operation of a controller withDTSE.

FIG. 7 is a diagram illustrating a Trigger Mapping Table.

FIG. 8 is a diagram illustrating a Sequence Configuration Table.

FIG. 9 is a diagram illustrating a Sequence Result Table.

FIG. 10 is a state machine diagram illustrating the operation of aTriggering mapping State Machine performed by the DTSE.

FIG. 11 is a state machine diagram illustrating the operation of aSequence Entry State machine performed by the DTSE.

FIG. 12 is a flowchart describing the operation of the DTSE.

DETAILED DESCRIPTION

In a traditional controller, the speed at which multiple analog signalscan be sampled affects multiple aspects of the device under control. Forexample, the control of a BLDC or PMSM motor is greatly affected by thespeed at which the motor controller can sample multiple analog signals.First, the sampling speed affects the speed at which the motorcontroller can turn the motor. Second, the sampling speed affects theresolution at which the controller can control the speed and torque ofthe BLDC or PMSM motor. Third, the sampling speed affects the resolutionat which the controller can control the precise output voltage of apower supply device.

Latency of the analog signal sampling is an important performancecharacteristic of a controller. If the latency of the analog signalsampling is too great, then the accuracy of the analog sampling isreduced. A reduction of analog sampling accuracy will not onlynegatively affect the ability of the controller to accurately controlthe motor or power supply, it may also affect the value of the endproduct and possibly cause an unsafe end product.

FIG. 1 is a diagram of a traditional MCU 1 without an auto-sequencer.The traditional MCU 1 includes analog input pins 2, multiplexer (MUX) 3,analog-to-digital converter (ADC) 4, processor 5, memory 6 and data bus7. In operation, the multiplexer 3 receives one or more analog signalsvia the analog input pins 2 and outputs a selected one of the analogsignals to the input terminal of ADC 4. ADC 4 then converts the analogsignal into a digital value that represents the amplitude of the analogsignal (ADC RESULT). In one example, the amplitude of the analog signalis measured in volts for voltage. In another example, the amplitude ofthe analog signal is measured in amperes for current. The ADC 4 isconfigured by the processor 5 via ADC CONFIG data. The processor 5starts the ADC process by sending a START OF CONVERSION signal to theADC 4. In response to receiving the START OF CONVERSION signal from theprocessor, the ADC 4 performs the analog-to-digital conversion. When theconversion is complete, the ADC 4 sends an END OF CONVERSION signal tothe processor 5 indicating that the conversion is complete. Theprocessor 5 then is required to perform the additional operation ofreading the ADC result from the ADC 4 and storing the ADC result intothe memory 6. An external system then is able to read the ADC result viadata bus 7. Once the ADC result is stored in memory 6, the processor 5has to start the process over again to sample another analog signal.

The operation of the traditional controller without an auto-sequencer isillustrated in FIG. 2. First the processor 5 must set the multiplexer 3to select the desired analog signal, send ADC CONFIG data to the ADC 4,and then send the START OF CONVERSION signal to the ADC 4. The ADC 4then starts the conversion of the single selected analog signal. Oncethe single conversion is completed, the ADC 4 sends an END OF CONVERSIONsignal to the processor 5. In response to receiving the END OFCONVERSION signal, the processor 5 is required to read the ADC resultfrom the ADC 4 and store the ADC result in the memory 6. Only once theprocessor 5 has finished the write operation of the ADC result to thememory 6, can the processor 5 begin to repeat the process for the nextdesired analog signal by resetting the multiplexer 3 and sending new ADCCONFIG data to setup the ADC 4 for the next conversion. FIG. 2illustrates that a controller without auto-sequencer can only convertone analog signal without requiring additional communication with, andprocessing by, the processor 5. This controller requires too manyprocessor cycles for each analog conversion performed for highperformance control applications.

FIG. 3 is a diagram illustrating the operation of a controller with anauto-sequencer. A more advanced type of controller includes a processingengine (MCU) and an auto-sequencer. An auto-sequencer allows multipleanalog channels to be converted sequentially as shown in FIG. 3. Some ofthe analog channels are determined to be “critical samples” and otheranalog channels are determined to be “non-critical samples”. The MCUmust set the multiplexer 3 to output the desired analog signal,configure the ADC 4, and configure the auto-sequencer to startperforming the desired conversions in the desired order. The MCU thensends the START OF CONVERSION signal to the ADC 4 to start theconversion sequence. In response to receiving the START OF CONVERSIONsignal, the ADC 4 performs each of the desired conversions sequentially.Once the final conversion is completed, the ADC 4 sends an END OFCONVERSION signal to the MCU. In response to receiving the END OFCONVERSION signal, the MCU must read the multiple ADC results from theADC 4 and then store the ADC results in memory 6 and perform thenecessary processing on the multiple ADC results to properly control themotor or power supply.

The controller with an auto-sequencer is an improvement over thetraditional controller as the controller with auto-sequencing reducesthe number of MCU cycles required for each analog sample. However, thecontroller with auto-sequencing still suffers from multiple drawbacks. Acontrol system usually has a set of analog samples that are critical tothe functioning of the control system and another set of analog samplesthat are non-critical to the functioning of the control system. Forexample, the motor current in the case of motor controller and outputvoltage in the case of power supplies are analog samples that arecritical to proper operation of the device under control. Alternatively,temperature is an example of a non-critical analog sample. Ideally, thenon-critical analog samples would be processed without causing any delayin the processing of critical analog samples. The controller withauto-sequencing illustrated in FIG. 3 cannot process critical analogsamples until all of the non-critical samples have been completed. Thissystem does not provide real-time availability of critical analogsamples to the MCU for processing and causes latency from when theanalog signals are sampled and when the MCU is able to process theanalog samples. An improved solution is needed to provide reducedlatency in the processing of critical analog samples.

FIG. 4 is a diagram of a controller with a Dynamic Triggering and SampleEngine (DTSE). Controller with DTSE 10 includes multiple analog inputspins 11, multiplexer 12, analog-to-digital (ADC) 13, DTSE 14, processor15 (optionally included), data bus 16, and trigger inputs 17. In oneexample, the DTSE 14 includes thirty-two input hardware triggers. Thetriggers may be any signal, such as Pulse Width Modulated (PWM), TimerCapture and Compare (CCR), software trigger or the like. The triggerinputs may be analog or digital signals. FIG. 5 is a more detaileddiagram the DTSE 14 of FIG. 4. The DTSE 14 includes a trigger mappingtable 30, a sequence configuration table 31, a sequence result table 32,and a state machine 33. The state machine 33 may be implemented usingcombinatory logic or may be implemented using a microcontroller.

It is noted herein that FIG. 4 is an illustration of example embodimentof the present invention where the DTSE 14 is fabricated on a singleintegrated circuit that also includes an analog-to-digital convertercircuit and a processor circuit. In other embodiments, the DTSE 14 maybe fabricated on a dedicated integrated circuit, where theanalog-to-digital converter circuit is located on a separate integratedcircuit, and the processor circuit is located on a separate integratedcircuit. In another example, the DTSE 14 may be fabricated on anintegrated circuit that also includes an analog-to-digital circuit or aprocessor circuit.

FIG. 7 is a diagram of the trigger mapping table. The trigger mappingtable includes a sequence configuration table entry number for eachtrigger input. In the event that trigger input number one is triggered,then the trigger mapping table indicates a sequence configuration tableentry number of one. In the event that the trigger input number two istriggered, then the trigger mapping table indicates a sequenceconfiguration table entry number of one. In the event that the triggerinput number three is triggered, then the trigger mapping tableindicates a sequence configuration table entry of one. In the event thatthe trigger input number four is triggered, then the trigger mappingtable indicates a sequence configuration table entry of six. In theevent that the trigger input number five is triggered, then the triggermapping table indicates a sequence configuration table entry of six. Inthe event that the trigger input number six is triggered, then thetrigger mapping table indicates a sequence configuration table entry oftwelve. In the event that the trigger input number seven is triggered,then the trigger mapping table indicates a sequence configuration tableentry of twelve. In the event that the trigger input number eight istriggered, then the trigger mapping table indicates a sequenceconfiguration table entry of eighteen. In this fashion, the triggermapping table can point multiple input trigger events to the same ordifferent sequence configuration table entries. This provides memorysavings in that redundant storage of sequence configurations areavoided. Rather, two separate trigger inputs that require the samesequence configuration can point to the same sequence configuration. Forexample, in the event that trigger inputs one, two and three all are forthe same BLDC or PMSM motor, each triggering event would require thesame sequence configuration to measure the same analog samples from eachelectrical motor. In this scenario, there is no need to store duplicatecopies of the single sequence configuration.

FIG. 8 is a diagram of the sequence configuration table. The sequenceconfiguration table includes an ADC conversion channel, an interrupt(IRQ) value, a signaling (EMUX) value, and a sequence complete indicatorfor each sequence configuration table entry number. In one example, theEMUX value may indicate a required change to the settings of the ADCmultiplexer 12 (shown in FIG. 4). In another example, the EMUX value mayindicate sample and hold time for ADC operation. In the event that thetrigger mapping table outputs a sequence configuration table entrynumber one, the sequence configuration table indicates that ananalog-to-digital conversion is to be performed on channel 0 (ADC0),that an interrupt (IRQ) is not to be performed, that external signaling(EMUX) is to be performed, and that the sequence is not completed. Inthe event that the trigger mapping table outputs a sequenceconfiguration table entry number five, the sequence configuration tableindicates that an analog-to-digital conversion is to be performed onchannel 4 (ADC4), that an interrupt (IRQ) is not to be performed, thatexternal signaling (EMUX) is not to be performed, and that the sequenceis completed. In this fashion, the sequence configuration table providesall the necessary configurations to perform a predeterminedanalog-to-digital conversion sequence.

FIG. 9 is a diagram of the sequence result table. The sequence resulttable includes an analog-to-digital (ADC) result for each sequenceconfiguration table entry number. In the event that the trigger mappingtable outputs a sequence configuration table entry number one, thesequence result table stores the analog-to-digital conversion performedon channel 0 (ADC0) in the corresponding ADC result field in thesequence result table. In the event that the trigger mapping tableoutputs a sequence configuration table entry number five, the sequenceresult table stores the analog-to-digital conversion performed onchannel 4 (ADC4) in the corresponding ADC result field in the sequenceresult table. This one to one mapping of sequence configuration tableentry numbers in the sequence configuration table and the sequenceresult table alleviates the need for a Direct Memory Access (DMA) designor a large number of transistors to perform a DMA-like hardware memorystorage without the use of the MCU. The user may configure the SequenceEntry Table and the Sequence Result Table to arrange the resultsoptimally for the MCU and application. The MCU has the ability to readfrom the sequence result table at any time.

In one example, DTSE 14 is configured by processor 15 via DTSE CONFIGsignal 21. DTSE CONFIG includes values stored in the various tableswithin the DTSE 14. In another example, the DTSE 14 can be configured byan external device that communicates a DTSE CONFIG signal 21 to the DTSE14 via data bus 16.

In operation, the DTSE 14 receives multiple trigger input signals viatrigger input pins 17. The DTSE monitors the signal present on eachtrigger input pin. The DTSE 14 detects a triggering event on any of thetrigger input pins. In one example, a high-to-low voltage transition isdefined as a triggering event. In another example, a low-to-high voltagetransition is defined as a triggering event. In yet another example,both a high-to-low and a low-to-high transition is defined as atriggering event. As discussed above, regarding FIG. 7, the DTSE 14 usesthe trigger mapping table to determine a sequence configuration tableentry number based on the triggered input.

The process performed by the trigger mapping state machine isillustrated in FIG. 10. The state machine starts at step 50. In step 51,the trigger mapping state machine determines if a triggering event isdetected on input number one. If a triggering event is detected, then asequence number is determined based on the trigger mapping table in step52. In one example, step 52 involves a lookup operation wherein thesequence number is returned based on the trigger input on which atriggering event was detected. In response to determining the sequencenumber, the state machine reads the sequence configuration values fromthe sequence configuration table that correspond to the sequence number.If a triggering event is not detected at step 51, then the state machinedetermines if a triggering event is detected on trigger input two instep 53. If a triggering event is detected, then a sequence number isdetermined based on the trigger mapping table in step 54. In response todetermining the sequence number, the state machine reads the sequenceconfiguration values from the sequence configuration table thatcorrespond to the sequence number. If a triggering event is not detectedat step 53, then the state machine determines if a triggering event isdetected on trigger input three in step 55. If a triggering event isdetected, then a sequence number is determined based on the triggermapping table in step 56. In response to determining the sequencenumber, the state machine reads the sequence configuration values fromthe sequence configuration table that correspond to the sequence number.The trigger mapping state machine continues in this fashion until eachtrigger input is checked. Once the last trigger input is checked for atriggering event, the trigger mapping state machine returns to step 51and begins the process anew.

Once a sequence entry is read from the sequence configuration table, thesequence entry state machine illustrated in FIG. 11 is started (step60). In step 61, it is determined if signaling (EMUX) is to be sentbefore sample and hold (S&H) is required. If so, then it is determinedif the signaling data (EMUX) has been sent in step 62. If the signalingdata has been sent, then it is determined if a sequence delay isrequired in step 63. If so, then it is determined if the delay hasexpired in step 64. If the delay has expired, then it is determined ifthe ADC sample and hold is complete in step 65. If so, then it isdetermined if signal is required after the ADC sample and hold iscomplete in step 66. If so, it is determined if the EMUX signaling datahas been sent in step 67. If the signaling data has been sent, then itis determined if the ADC conversion is still pending in step 68. If not,then it is determined if the ADC interrupt (IRQ) is completed in step69. If so, then it is determined if the sequence is done in step 70. Ifthe sequence is done, then the process is complete and the sequenceentry state machine waits for the next triggering event. If the sequenceis not done, then the state machine advances to the next sequence andgoes back to step 60.

The operation of the controller with DTSE is illustrated in FIG. 6 inconjuncture with FIGS. 4 and 5. First, the DTSE 14 detects a triggerevent on one of the trigger input pins 17. As discussed above, using thetrigger mapping table the DTSE 14 determines a sequence entry numberthat is associated with the trigger input. The DTSE 14 then uses thesequence entry number to read a particular set of sequence configurationvalues from the sequence configuration table. The DTSE 14 then uses thesequence configuration information to configure multiplexer 12, ADC 13and send any required interrupts or data to processor 15. Once themultiplexer 12 and ADC 13 are properly configured, the DTSE 14 sends aSTART OF CONVERSION signal to the ADC 13. It is important to point outthat the START OF CONVERSION signal is sent by the DTSE 14 not theprocessor 15 (MCU). This allows the analog sampling process to beginwithout disrupting the processing performed by the processor 15 orwaiting (latency) for the processor 15 to complete a pending processbefore starting the analog-to-digital conversion. In response toreceiving the START OF CONVERSION signal, the ADC 13 begins the sequenceof analog-to-digital conversions. In the example illustrated in FIG. 6,the first two analog samples of the sequence are determined to becritical and the last two analog samples of the sequence are determinedto be non-critical. This means that in an ideal situation, the processor15 would be able to begin processing the critical analog samples beforethe non-critical analog samples are completed. The DTSE 14 achieves thisdesign goal by issuing an interrupt to the processor 15 indicating theADC result for the critical analog samples are available in the sequenceresult table for processing before the non-critical samples arecompleted. In this fashion, the processor 15 is able to process criticalanalog samples immediately without waiting for the non-critical analogsamples included in the sequence to be completed. Once the non-criticalanalog samples are completed, the DTSE 14 may issue a second interrupt(IRQ #2) to the processor 15 indicating that the non-critical analogsamples are ready for processing.

In one embodiment, the DTSE outputs an interrupt signal after thecompletion of each sample. In another embodiment, the DTSE outputs afirst interrupt after all critical samples are completed and a secondinterrupt after all non-critical samples are completed. The method inwhich the DTSE outputs interrupt signals is controlled by the IRQ(interrupt) value programmed into the sequence configuration table. TheDTSE interrupt operation can be changed by updating the IRQ value storedin the sequence configuration table for a given sequence configurationtable entry number.

Another advantage provided by the controller with DTSE is that the DTSEmay start another sequence of conversions before the processor completesprocessing of analog samples from the previous sequence of conversions.In this fashion, the DTSE can start the next sequence promptly after thetermination of the previous sequence, such that the critical samples ofthe next sequence are available for processing as soon as the processorfinished processing of the previous sequence of analog samples. Thisallows the processor to process analog samples in the most efficientmanner without wasting cycles determining configuration settings,controlling multiplexer and ADC configuration, and ADC result storagemanagement.

FIG. 12 is a flowchart describing the operation of the DTSE. In step100, the DTSE detects a first trigger received on a trigger input. Thefirst trigger triggers a series of analog-to-digital conversions to becompleted by the ADC circuit. In step 101, the DTSE determines a firstsequence configuration stored in a sequence configuration table that isassociated with the first trigger. In step 102, the DTSE causes a firstanalog-to-digital conversion to be performed using the first sequenceconfiguration. In step 103, the DTSE causes an analog-to-digitalconversion result value to be stored in a sequence result table. In step104, the DTSE outputs an interrupt to a processor indicating that thefirst analog-to-digital conversion is complete and that the result valueis available in the sequence result table. The interrupt is outputbefore at least one of the remaining analog-to-digital conversions inthe series is completed.

Although certain specific embodiments are described above forinstructional purposes, the teachings of this patent document havegeneral applicability and are not limited to the specific embodimentsdescribed above. Accordingly, various modifications, adaptations, andcombinations of various features of the described embodiments can bepracticed without departing from the scope of the invention as set forthin the claims.

What is claimed is:
 1. An integrated circuit, comprising: a hardwaretrigger input; a memory that stores a trigger mapping table and asequence configuration table; and a state machine, wherein the statemachine is configured to: detect a trigger received on the hardwaretrigger input, wherein the trigger triggers a series ofanalog-to-digital conversions to be completed by an analog-to-digitalconverter circuit, wherein the analog-to-digital conversions includecritical samples and non-critical samples; determine a sequenceconfiguration stored in the sequence configuration table that isassociated with the trigger; and cause one of the analog-to-digitalconversions to be performed using the sequence configuration, wherein atleast one of the critical samples is performed before at least one ofthe non-critical samples.
 2. The integrated circuit of claim 1, whereinthe state machine is also configured to output an interrupt indicatingthat the analog-to-digital conversion has been completed by theanalog-to-digital circuit.
 3. The integrated circuit of claim 2, whereinthe interrupt is output before at least one of the remaininganalog-to-digital conversions in the series is completed.
 4. Theintegrated circuit of claim 2, wherein the interrupt is output after atleast one of the critical samples of the series of analog-to-digitalconversions is completed.
 5. The integrated circuit of claim 2, whereinthe interrupt is output after at least one of the non-critical samplesof the series of analog-to-digital conversions is completed.
 6. Theintegrated circuit of claim 1, wherein the memory also stores a sequenceresult table.
 7. The integrated circuit of claim 6, wherein the statemachine is also configured to cause a analog-to-digital conversionresult value to be stored in the sequence result table.
 8. Theintegrated circuit of claim 6, wherein each sequence configurationstored in memory is associated with a unique entry in the sequenceresult table.
 9. The integrated circuit of claim 1, wherein the triggermapping table is programmed by another device via a bus terminal. 10.The integrated circuit of claim 9, wherein the bus is an AdvancedMicrocontroller Bus Architecture (AMBA) bus.
 11. The integrated circuitof claim 1, wherein the integrated circuit is configurable to detect arising edge of a Pulse Width Modulate (PWM) signal on the hardwaretrigger input or a Pulse Width Modulate (PWM) signal on the hardwaretrigger input.
 12. The integrated circuit of claim 1, wherein the statemachine is implemented using a microcontroller.
 13. The integratedcircuit of claim 1, wherein the state machine is implemented usingcombinatory logic.
 14. The integrated circuit of claim 1, wherein theintegrated circuit includes a plurality of hardware trigger inputs. 15.The integrated circuit of claim 1, wherein the memory comprises aplurality of storage devices.
 16. A method, comprising: (a) detecting atrigger received on a hardware trigger input, wherein the triggertriggers a series of analog-to-digital conversions to be completed by ananalog-to-digital converter circuit, and wherein the series ofanalog-to-digital conversions includes critical conversions andnon-critical conversions; (b) determining a sequence configurationstored in a sequence configuration table that is associated with thetrigger; (c) causing an analog-to-digital conversion to be performedusing the sequence configuration; (d) causing an analog-to-digitalconversion result value to be stored in a sequence result table; and (e)outputting an interrupt indicating that the analog-to-digital conversionresult value is available in the sequence result table, wherein theinterrupt is output before at least one of the non-critical conversionsin the series is completed.
 17. The method of claim 16, wherein (a)through (e) are performed by a state machine in a Dynamic Triggering andSample Engine (DTSE).
 18. An apparatus comprising: a hardware triggerinput; and means for detecting a trigger received on the hardwaretrigger input, wherein the trigger triggers a series ofanalog-to-digital conversions to be completed by an analog-to-digitalconverter circuit, wherein the analog-to-digital conversions includecritical samples and non-critical samples, wherein the means is also forcausing at least one of the critical samples to be performed before atleast one of the non-critical samples.
 19. The apparatus of claim 18,wherein the means is a state machine of a Dynamic Triggering and SampleEngine (DTSE).
 20. The apparatus of claim 18, wherein the means is alsofor determining a sequence configuration stored in a sequenceconfiguration table that is associated with the trigger, and wherein themeans is also for outputting an interrupt indicating that ananalog-to-digital conversion has been completed by the analog-to-digitalcircuit.